14.4.2.2 Status Register: Master-Receiver Mode

Table 14-9. STATUS Register – Master-Receiver Mode
Status CodeStatusData Register ActionControl Register BitsNext Action Taken by Core
STASTOSIAA
0x08A START condition is transmitted.Load SLA+R—00—SLA+R is transmitted; ACK is received
0x10A repeated START condition is transmitted.Load SLA+R—00—SLA+R is transmitted; ACK is received
Load SLA+W—00—SLA+W is transmitted; I2C is switched to MST/TRX mode.
0x38Arbitration lost in not ACK (NACK) bit.No action000—The bus is released; I2C enters the Slave mode.
100—A start condition is transmitted when the bus gets free.
0x40SLA+R has been transmitted; ACK is received.No action0000Data byte is received; not ACK (NACK) is returned.
0001Data byte is received; ACK is returned
0x48SLA+R is transmitted; not ACK (NACK) is received.No action100—Repeated START condition is transmitted
010—STOP condition is transmitted; STO flag is reset.
110—STOP condition followed by a START condition is transmitted; STO flag is reset.
0x50Data byte has been received; ACK is returned.Read data byte0000Data byte is received; not ACK(NACK) is returned.
Read data byte0001Data byte is received; ACK is returned
0x58Data byte is received; not ACK (NACK) is returned.Read data byte100—Repeated START condition is transmitted
Read data byte010—STOP condition is transmitted; STO flag is reset.
Read data byte110—STOP condition followed by a START condition is transmitted; STO flag is reset.
0xD0SMBus master reset is activated.No action0—Wait 35 ms for interrupt to set, clear interrupt and proceed to F8H state.

Notes:

  • SLA = Slave address
  • SLV = Slave
  • REC = Receiver
  • TRX = Transmitter
  • SLA+W = Master sends slave address then writes data to slave
  • SLA+R = Master sends slave address then reads data from slave