14.4.2.1 Status Register: Master-Transmitter Mode

Table 14-8. Status Register – Master-Transmitter Mode
Status Code	Status	Data Register Action	Control Register Bits				Next Action Taken by Core
Status Code	Status	Data Register Action	STA	STO	SI	AA	Next Action Taken by Core
0x08	A START condition is transmitted.	Load SLA+W		0	0		SLA+W is transmitted; ACK is received.
0x10	A repeated START condition is transmitted.	Load SLA+W		0	0		SLA+W is transmitted; ACK is received.
0x10	A repeated START condition is transmitted.	Load SLA+R		0	0		SLA+R is transmitted; Core is switched to MST/REC mode.
0x18	SLA+W is transmitted; ACK is received.	Load data byte	0	0	0		Data byte is transmitted; ACK is received.
		No action	1	0	0		Repeated START is transmitted.
			0	1	0		STOP condition is transmitted; STO flag is reset.
			1	1	0		STOP condition followed by a START condition is transmitted; STO flag is reset.
0x20	SLA+W is transmitted; not ACK (NACK) is received.	Load data byte	0	0	0		Data byte is transmitted; ACK is received.
		No action	1	0	0		Repeated START is transmitted.
			0	1	0		STOP condition is transmitted; STO flag is reset.
			1	1	0		STOP condition followed by a START condition is transmitted; STO flag is reset.
0x28	Data byte in Data Register is transmitted; ACK is received.	Load data byte	0	0	0		Data byte is transmitted; ACK bit is received.
		No action	1	0	0		Repeated START is transmitted.
			0	1	0		STOP condition is transmitted; STO flag is reset.
			1	1	0		STOP condition followed by a START condition is transmitted; STO flag is reset.
0x30	Data byte in Data Register is transmitted; not ACK (NACK) is received.	Data byte	0	0	0		Data byte is transmitted; ACK is received.
		No action	1	0	0		Repeated START is transmitted.
			0	1	0		STOP condition is transmitted; STO flag is reset.
			1	1	0		STOP condition followed by a START condition is transmitted; STO flag is reset.
0x38	Arbitration lost in SLA+R/W or data bytes.	No action	0	0	0		The bus is released; not-addressed Slave mode is entered.
0x38	Arbitration lost in SLA+R/W or data bytes.	No action	1	0	0		A START condition is transmitted when the bus gets free.
0xD0	SMBus master reset is activated.	No action					Wait 35 ms for interrupt to be set, clear interrupt and proceed to F8H state.

Important:

SLA = Slave address
SLV = Slave
REC = Receiver
TRX = Transmitter
SLA+W = Master sends slave address then writes data to slave
SLA+R = Master sends slave address then reads data from slave