14.4.2.4 Status Register – Slave-Transmitter Mode
| Status Code | Status | Data Register Action | Control Register Bits | Next Action Taken by Core | |||
|---|---|---|---|---|---|---|---|
| STA | STO | SI | AA | ||||
| 0xA8 | Own SLA+R is received; ACK is returned. | Load data byte | 0 | 0 | 0 | Last data byte is transmitted; ACK is received | |
| 0 | 0 | 1 | Data byte is transmitted; ACK is received | ||||
| 0xB0 | Arbitration lost in SLA+R/W as master; own SLA+R is received; ACK is returned. | Load data byte | 0 | 0 | 0 | Last data byte is transmitted; ACK is received | |
| 0 | 0 | 1 | Data byte is transmitted; ACK is received | ||||
| 0xB8 | Data byte is transmitted; ACK is received. | Load data byte | 0 | 0 | 0 | Last data byte is transmitted; ACK is received | |
| 0 | 0 | 1 | Data byte is transmitted; ACK is received | ||||
| 0xC0 | Data byte is transmitted; not ACK (NACK) is received. | No action | 0 | 0 | 0 | 0 | Switched to not-addressed SLV mode; no recognition of own SLA or general call address. |
| 0 | 0 | 0 | 1 | Switched to not-addressed SLV mode; own SLA or general call address is recognized. | |||
| 1 | 0 | 0 | 0 | Switched to not-addressed SLV mode; no recognition of own SLA or general call address; START condition is transmitted when the bus gets free. | |||
| 1 | 0 | 0 | 1 | Switched to not-addressed SLV mode; own SLA or general call address is recognized; START condition is transmitted when the bus gets free. | |||
| 0xC8 | Last data byte is transmitted; ACK is received. | No action | 0 | 0 | 0 | 0 | Switched to not-addressed SLV mode; no recognition of own SLA or general call address. |
| 0 | 0 | 0 | 1 | Switched to not-addressed SLV mode; own SLA or general call address is recognized. | |||
| 1 | 0 | 0 | 0 | Switched to not-addressed SLV mode; no recognition of own SLA or general call address; START condition is transmitted when the bus gets free. | |||
| 1 | 0 | 0 | 1 | Switched to not-addressed SLV mode; own SLA or general call address is recognized; START condition is transmitted when the bus gets free. | |||
| 0xD8 | 25 ms SCL low time is reached; device must be reset. | No action | 0 | Slave must proceed to reset state by clearing the interrupt within 10 ms, according to SMBus specification v2.0. | |||
Notes:
- SLA = Slave address
- SLV = Slave
- REC = Receiver
- TRX = Transmitter
- SLA+W = Master sends slave address then writes data to slave
- SLA+R = Master sends slave address then reads data from slave