12.2.4.3.1 Break/Sync Detection

When the LIN header detection block is enabled with the ELIN bit (Table 12-22), the LIN circuit automatically detects break fields greater than 11 Tbits (bit time) of the currently running baud rate. The LIN circuit calculates the number of APB clock cycles from the first sync byte falling edge to the fifth (and last) sync byte falling edge with a 23-bit counter. The 23-bit counter is necessary to count eight Tbits at the slowest baud rate. Once the fifth edge is detected, the LIN circuit automatically updates the integer and fractional divisor registers and the PID and rest of the frame can be handled with the normal UART Rx/Tx paths. Every LIN frame begins with the break, which comprises of break lengths greater than 11 Tbits.

This serves as a start-of-frame notice to all nodes on the bus. The following figure shows the break field signals the start of a new frame.

The sync field is the second field transmitted by the master task in the header. Sync is defined as the character x55. The sync field allows slave devices that perform automatic baud rate detection to measure the period of the baud rate and adjust their internal baud rates to synchronize with the bus. The sync field allows for fine calibration of the nominal baud rate, as shown in the following figure. After the LINBI bit is set in multi-mode interrupt register (Table 12-16), the first falling edge resets the sync timer and the fifth falling edge stops counting. The 23-bit count value is divided by 128 (128 = 16 baud clocks per bit X 8 bits) to generate the integer baud rate by shifting the count value by seven towards LSB. The fractional value is contained in the remaining bits, using the first insignificant bit to round the result.

The PID field is the final field transmitted by the master task in the header. This field provides identification for each message on the network and ultimately determines which nodes in the network receive or respond to each transmission. All slave tasks continually listen for PID fields, verify their parities, and determine if they have to receive data or send data for this particular identifier. The LINSI interrupt resets the FIFO address pointers so that the PID stays in the first location. The firmware reading the PID byte determines if the application needs to send or receive data, and the trigger level that needs to be set. A PID parity error check is performed on the fly and the interrupt, PID_PEI, is asserted when there is a mismatch between the incoming P0 and P1 parity bits and the calculated P0 and P1 parity.

The following figure shows the PID field processed as the first byte and placed in the receive FIFO. The parity is calculated as per the equations shown, and an interrupt (PID_PEI) is generated, if there is a mismatch between the calculated PID parity and the received PID parity.