12.2.4.8 9-bit Transmit/Receive Mode

MMUART_x supports 9-bit address flag capability. The 9th bit mode is required for multi-drop addressing topologies. Addressing mode is essentially 8-bit mode with 1 parity error bit or the 9th bit with parity set at stick 0, which means that the parity is permanently set to 0 while receiving or transmitting data. The following figure shows an error condition of 1 is used as an address flag.

Figure 12-18. 9-Bit Format

There are two ways to handle 9-bit multi-drop addressing:

  • Software Driven Parity Error Checking: This is accomplished by configuring the MMUART in 
8-bit mode, with stick 0 parity (SP bit in Table 12-17) enabled. A parity error (PE) in the line status register (Table 12-19) is set whenever an address flag (AF) arrives by marking the address. Software then checks this address byte to see if it matches its own address, and then proceed accordingly.
  • Automatic Hardware Address Flag Comparison: When the automatic address flag comparison option is enabled with the EAFM bit in the Multi-mode register 2 (Table 12-24), the MMUART initially disables the Rx FIFO and continuously checks for the address flag. If an address flag is received and the associated 8-bit data matches the address in the Table 12-28 register, the Rx FIFO is enabled. In this mode, the software does not check the address, and only receives Rx data once the address is matched. Disabling the Rx FIFO occurs either by address flag being re-sent with a non-matching address value (automatic), or the EAFC bit in Table 12-24 is set. An example for using EAFC takes place when the address flag is received with the correct address. If the frame length is known to be 4 bytes, then the software could set the EAFC bit to disable the Rx FIFO after the 4th received byte, and begin searching for another address flag with matching address.