12.4.9 Multi-Mode Interrupt Identification Register (IIM)

Table 12-16. IIM
Bits	Name	R/W	Description
[7:5]	Reserved	Clean on R	Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation.
4	LINSI	Clean on R	LIN sync detection interrupt ID. This bit is set when 5^th falling edge is detected by the sync timer. It resets the FIFO address pointers so that PID will be in the first location. Reading the Table 12-16 register clears this interrupt.
3	LINBI	Clean on R	LIN break interrupt, set automatically when break length of 11.5 Tbits is detected. Reading the Table 12-16 register clears this interrupt.
2	PID_PEI	Clean on R	Protected Identifier Field (PID) parity error interrupt is generated when there is a mismatch in PID in LIN header, that is, when either the P0 or P1 bits in the incoming PID byte do not match the calculated P0 and P1 error.
1	NACKI	Clean on R	NACK interrupt is asserted when EERR bit is set in Table 12-24. Reading the Table 12-24 clears the interrupt.
0	RTOII	Clean on R	Receiver Time Out (RTO) interrupt ID. RTO interrupt is asserted when RTO value is reached by the counter. It gets cleared when writing to the RTO register.

[7:5]

Reserved

Clean on R

0

Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation.

4

LINSI

Clean on R

0

LIN sync detection interrupt ID. This bit is set when 5^th falling edge is detected by the sync timer. It resets the FIFO address pointers so that PID will be in the first location. Reading the Table 12-16 register clears this interrupt.

3

LINBI

Clean on R

0

LIN break interrupt, set automatically when break length of 11.5 Tbits is detected. Reading the Table 12-16 register clears this interrupt.

2

PID_PEI

Clean on R

0

Protected Identifier Field (PID) parity error interrupt is generated when there is a mismatch in PID in LIN header, that is, when either the P0 or P1 bits in the incoming PID byte do not match the calculated P0 and P1 error.

1

NACKI

Clean on R

0

NACK interrupt is asserted when EERR bit is set in Table 12-24. Reading the Table 12-24 clears the interrupt.

0

RTOII

Clean on R

0

Receiver Time Out (RTO) interrupt ID. RTO interrupt is asserted when RTO value is reached by the counter. It gets cleared when writing to the RTO register.