23.7.1.1.3 FPGA Fabric Address Regions (MSS Master View)

Up to six different memory regions can be assigned to each FIC in the MSS memory map. By default, fabric regions 0, 1, and 2 are accessible through FIC_0, and regions 3, 4, and 5 are accessible through FIC_1 as shown in the following figure.

Figure 23-16. FPGA Fabric Address Regions (MSS Master View)

Important: This option is available in FIC_0 configurator only. If memory regions are required to be configured to FIC_1, the FIC_0 configurator needs to be opened.

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