6.1.4.1.3 Ensuring Deterministic Latency

If the system designer wishes to have deterministic latencies of ISR execution, the ISRs need to be located in eSRAM. The eSRAM must be un-contended to ensure true determinism. A maximum latency value can be programmed to eSRAM slaves, so processor masters do not wait long for access to eSRAM slaves. The maximum latency is set by writing into SW_MAX_LAT_ESRAM0[2:0] or SW_MAX_LAT_ESRAM1 of ESRAM_MAX_LAT. You can execute code from the external memory (SRAM or DDR). DDR is accessed by the Cortex-M3 processor masters directly through the cache controller block and not through the AHB bus matrix block.