10.2.1.5 SGMII Module

The SGMII module provides an SGMII that facilitates a connection between any IEEE 802.3 standard GMII or MII interface and an SGMII interface that is compliant with version 1.7 of the SGMII specification.

The SGMII module uses TBI to provide the 8B/10B encoding, decoding, and auto-negotiation functionality that is defined in Clause 36 of the IEEE 802.3z specification. This allows link partners to synchronize with each other and exchange information regarding their configuration capabilities, using a symbol stream that has a proven industry standard. The SGMII also instantiates transmit and receive conversion and rate adaptation modules, which allow for G/MII data/control conversion, half-duplex control encoding, and clock domain interfacing to the SGMII clock domain. The SGMII core includes optional modules for 10-bit comma alignment.

Both transmit and receive paths leverage the physical coding sub-layer and the auto-negotiation sub-layers of the IEEE 802.3z specification, as explained in clauses 36 and 37. In the transmit direction, the 10-bit encoded data is serialized and output over the interface. In the receive direction, the single-bit input is made parallel after being aligned to comma characters.

The SGMII core also includes support for MAC speeds less than gigabit rates. To maintain a constant clock frequency at the PHY interface for all MAC speeds, the MII bus data is replicated internally to maintain a gigabit rate at the output of the SGMII core.

TSEMAC can have separate clocks for MSS and PHY side connections. These clocks are asynchronous to each other.