20.2.6.2.1 MDDR_AXI_RESET_N

MDDR_AXI_RESET_N is generated from FPGA fabric reset input (MDDR_DDR_CORE_RESET_N), SYSRESET_N, and the MDDR soft reset (MDDR_CTLR_SOFTRESET) from SYSREG.

The following figure shows the generation of MDDR_AXI_RESET_N.

Figure 20-16. MDDR_AXI_RESET_N Generation

The Reset Controller drives a synchronized reset to AXI logic in the MDDR.

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