20.2.6.2.2 MDDR_APB_RESET_N
MDDR_APB_RESET_N is generated from FPGA fabric PRESET input (MDDR_APB_S_RESET_N) or SYSRESET_N, based on the selection of MDDR_CONFIG_LOCAL in SYSREG. The MDDR_CONFIG_LOCAL bit is in the MDDR configuration register (MDDR_CR as defined in Table 20-4) of SYSREG.
The following figure shows the generation of MDDR_APB_RESET_N.
The Reset Controller drives a synchronized reset to the APB logic of the MDDR subsystem.