9.3.3 USB OTG Controller Clocks and Resets
The following conditions are to be considered in the design for clocks and resets while using the USB OTG controller:
- To operate the USB OTG controller correctly with the external USB PHY device, the MSS FCLK and AHB CLK must be configured to run at greater than 30 MHz.
- To reset the external USB PHY, it is necessary to use an MSS GPIO port. Firmware resets the USB PHY whenever there is a USB controller reset done by the USB soft reset register settings.
- The USB controller resets on power-up and is held in reset until it is enabled. The USB controller can be reset by writing to USB_SOFTRESET field of the SOFTRESET_REG at address 0x40038048, located in the SYSREG block. The USB firmware drivers implements this feature.
| Register Name | Address | Bit Number | Name | Reset Value | Function |
|---|---|---|---|---|---|
| 9.3.9.18 SOFT_RESET_REG Bit Definitions (Table 9-81) | 0x40038048 | 14 | USB_SOFTRESET | 0x1 | Controls reset input to the USB controller 0: Release USB controller from reset 1: Keep USB controller in reset (reset value) |
At power-up this bit is asserted as 1. This keeps the USB controller in a Reset state. If the bit is set to 0, the USB controller is allowed to become active. If USB_SOFTRESET is 0, the USB controller can be held in Reset by other system reset sources.