9.3.7 FIFO Registers
These registers provide access to endpoint transmit and receive FIFOs. Writing to these addresses loads data into the transmit for the corresponding endpoint. Reading from these addresses unloads data from the receive FIFO for the corresponding endpoint.
| Register Name | Address Offset from 0x40043000 | Width | R/W Type | Reset Value | Description |
|---|---|---|---|---|---|
| EP0_FIFO_REG | 0x0020 | 32 | RW | 0 | Writing to this address loads data into the endpoint0 transmit FIFO. Reading from this address unloads data from the endpoint0 transmit FIFO. |
| EP1_FIFO_REG | 0x0024 | 32 | RW | 0 | Writing to this address loads data into the endpoint1 transmit FIFO. Reading from this address unloads data from the endpoint1 transmit FIFO. |
| EP2_FIFO_REG | 0x0028 | 32 | RW | 0 | Writing to this address loads data into the endpoint2 transmit FIFO. Reading from this address unloads data from the endpoint2 transmit FIFO. |
| EP3_FIFO_REG | 0x002C | 32 | RW | 0 | Writing to this address loads data into the endpoint3 transmit FIFO. Reading from this address unloads data from the endpoint3 transmit FIFO. |
| EP4_FIFO_REG | 0x0030 | 32 | RW | 0 | Writing to this addresses loads data into the endpoint4 transmit FIFO. Reading from this address unloads data from the endpoint4 transmit FIFO. |