9.3.9 ULPI and Configuration Registers
These registers correspond to the ULPI interface and link specific. This section covers all registers in this category along with the address offset, functionality, and per bit details.
| Register Name | Address | Width | R/W Type | Reset Value | Description |
|---|---|---|---|---|---|
| Table 9-64 | 0x40043070 | 8 | R | 0 | ULPI PHYs can use an external charge pump to
generate VBus rather than an internal charge pump. This register allows
selection of the external charge pump. It also allows this selection to be
displayed through an external VBus indicator. This register is read back from the PHY clock domain. Therefore, these bits do not return the updated values when the PHY is suspended. |
| Table 9-65 | 0x40043071 | 8 | R | 0 | Provides the basic control needed by ULPI-compatible PHYs when interfacing with in-car CarKit systems. |
| Table 9-66 | 0x40043072 | 8 | R | 0 | Enables the assertion of MC_NINT in response to the possible interrupt sources. |
| Table 9-67 | 0x40043073 | 8 | R | 0 | This register shows the unmasked value of the possible interrupt sources. |
| Table 9-68 | 0x40043074 | 8 | R | 0 | Contains the data associated with register reads/writes that are conducted through the ULPI interface. |
| Table 9-69 | 0x40043075 | 8 | R | 0 | Contains the address of the register being read/written through the ULPI interface. |
| Table 9-70 | 0x40043076 | 8 | R | 0 | Contains control and status bits relating to the register being read/written through the ULPI interface. |
| Table 9-71 | 0x40043077 | 8 | R | 0 | This register is used in Asynchronous modes to sample the ULPI bus and in Synchronous mode to store the last received command. |
| Table 9-74 | 0x40043078 | 8 | R | 0 | Allows read-back of the number of transmit and receive endpoints included in the design. |
| Table 9-75 | 0x40043079 | 8 | R | 0 | Provides information about the number of DMA channels and the width of the RAM. |
| Table 9-76 | 0x4004307A | 8 | RW | 0x5C | Allows configuration of link-specific delays. |
| Table 9-77 | 0x4004307B | 8 | RW | 0x3C | This register allows setting duration of the Vbus pulsing charge. |
| Table 9-78 | 0x4004307C | 8 | RW | 0x80 | Sets the minimum time gap that is allowed between the start of the last transaction and the EOF for high-speed transactions. |
| Table 9-79 | 0x4004307D | 8 | RW | 0x77 | Sets the minimum time gap that is to be allowed between the start of the last transaction and the EOF for full speed transactions. |
| Table 9-80 | 0x4004307E | 8 | RW | 0x72 | Sets the minimum time gap that is allowed between the start of the last transaction and the EOF for low-speed transactions. |
| Table 9-81 | 0x4004307F | 8 | RW | 0 | Asserts the output reset signals, NRSTO and NRSTOX, low. This register is self clearing and is reset by the input NRST. |