9.3.9.18 SOFT_RESET_REG Bit Definitions

Table 9-81. SOFT_RESET_REG (0x4004307F)
Bit Number	Name	Reset Value	Function
[7:2]	Reserved	N/A
1	NRSTX	0	The default value of this bit is 0. When a 1 is written to this bit, the output NRSTXO is asserted (low) within a minimum delay of seven cycles of the CLK input. The output NRSTXO is asynchronously asserted and synchronously deasserted with respect to XCLK. This register is self clearing and is reset by the input NRST.
0	NRST	0	The default value of this bit is 0. When a 1 is written to this bit, the output NRSTO is asserted (Low) within a minimum delay of seven cycles of the CLK input. The output NRSTO is asynchronously asserted and synchronously deasserted with respect to CLK. This register is self clearing and is reset by the input NRST.

[7:2]

Reserved

N/A

1

NRSTX

0

The default value of this bit is 0. When a 1 is written to this bit, the output NRSTXO is asserted (low) within a minimum delay of seven cycles of the CLK input. The output NRSTXO is asynchronously asserted and synchronously deasserted with respect to XCLK. This register is self clearing and is reset by the input NRST.

0

NRST

0

The default value of this bit is 0. When a 1 is written to this bit, the output NRSTO is asserted (Low) within a minimum delay of seven cycles of the CLK input. The output NRSTO is asynchronously asserted and synchronously deasserted with respect to CLK. This register is self clearing and is reset by the input NRST.