9.3.10 Non-Indexed End Point Control/Status Registers

The registers available at 10h–1Fh are accessible independently of the setting of the Index register. 100h–10Fh for EP0 registers; 110h–11Fh for EP1 registers; 120h–12Fh for EP2; and so on until EP4. For each set, a separate table for registers is included. Since all registers are similar except for address offset, a common bit definition table is included for each register.