9.3.6 Indexed Registers
This section covers all the registers in this category along with the address offset, functionality, and per- bit details. The registers mapped into this section depend on whether the core is in Peripheral mode (DEV_CTRL_REG.Bit2 = 0) or in Host mode (DEV_CTRL_REG.Bit2 = 1) and the value of the Index register (INDEX_REG).
| Register Name | Address | Width | R/W Type | Reset Value | Description |
|---|---|---|---|---|---|
| Table 9-23 | 0x40043010 | 16 | RW | 0 | Maximum packet size of host transmit endpoint. (Index register set to select endpoints 1 – 4 only). |
| Table 9-24 Table 9-25 | 0x40043012 | 8 | RW | 0 | Provide control and status bits for endpoint0 (Index register set to select endpoint0) and transmit endpoint0 (Index register set to select endpoints 1 – 4). The interpretation of the register depends on whether the USB controller is acting as a peripheral or a host. The value returned when the register is read reflects the status attained; for example, as a result of writing to the register. |
| Table 9-26 | 0x40043013 | 8 | RW | 0 | Provides control and status bits for endpoint0 (Index register set to select endpoint0) and transmit endpoint0 (Index register set to select endpoints 1 – 4). The interpretation of the register depends on whether the USB controller is acting as a peripheral or a host. The value returned when the register is read reflects the status attained; for example, as a result of writing to the register. |
| Table 9-32 | 0x40043014 | 16 | RW | 0 | Defines the maximum amount of data that can be transferred through the selected receive endpoint in a single operation. There is one such register for each receive endpoint (except endpoint 0). |
| Table 9-33 | 0x40043016 | 8 | RW | 0 | Provide control and status bits for transfers through the currently selected receive endpoint. There is one such register for each configured receive endpoint (not including endpoint 0). The interpretation of the register depends on whether the USB controller is acting as a peripheral or a host. The value returned when the register is read reflects the status attained; for example, as a result of writing to the register. |
| Table 9-35 | 0x40043017 | 8 | RW | 0 | Provides control and status bits for transfers through the currently-selected receive endpoint (Index register set to select endpoints 1 – 4 only). There is one such register for each configured receive endpoint (not including endpoint 0). The interpretation of the register depends on whether the USB controller is acting as a peripheral or a host. The value returned when the register is read reflects the status attained; for example, as a result of writing to the register. |
| Table 9-38 | 0x40043018 | 7 | R | 0 | Indicates the number of received data bytes in the endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while RxPktRdy (CSR0L_REG.bit0) is set. |
| Table 9-39 | 0x40043018 | 14 | R | 0 | Holds the number of data bytes in the packet currently in line to be read from the Rx FIFO. If the packet is transmitted as multiple bulk packets, the number given will be for the combined packet. The value returned changes as the FIFO is unloaded and is only valid while RxPktRdy (CSR0L_REG.bit0) is set. |
| Table 9-40 | 0x4004301A | 8 | RW | 0 | Applicable in Host mode only. Number of received bytes in endpoint0 FIFO (Index register set to select endpoint 0). |
| Table 9-41 | 0x4004301A | 8 | RW | 0 | Number of bytes to be read from the peripheral receive endpoint FIFO (Index register set to select endpoints 1 – 4). |
| Table 9-42 | 0x4004301B | 5 | RW | 0 | Sets the NAK response timeout on endpoint 0 (Index register set to select endpoint 0). |
| Table 9-43 | 0x4004301B | 8 | RW | 0 | Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host transmit endpoint (Index register set to select endpoints 1 – 4 only). |
| Table 9-45 | 0x4004301C | 8 | RW | 0 | Sets the transaction protocol, speed, and peripheral endpoint number for the host receive endpoint (Index register set to select endpoints 1 – 4 only). |
| Table 9-46 | 0x4004301D | 8 | RW | 0 | Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host receive endpoint (Index register set to select endpoints 1 – 4 only). |
| Table 9-47 | 0x4004301F | 8 | R | Returns details of USB controller configuration (Index register set to select endpoint 0). | |
| Table 9-48 | 0x4004301F | 8 | R | Returns the configured size of the selected receive and transmit FIFOs (endpoints 1 – 4 only). |