9.3.8 Control and Status Registers (OTG, Dynamic FIFO, and Version)
This section covers all registers in this category along with the address offset, functionality, and per bit details.
| Register Name | Address Offset from 0x40043000 | Width | R/W Type | Reset Value | Description |
|---|---|---|---|---|---|
| Table 9-52 | 0x0060 | 8 | R | 0x80 | Selects whether the USB controller operates in Peripheral mode or in Host mode, and also controls and monitors the USB VBus line. If the PHY is suspended, no PHY clock (XCLK) is received and the VBus is not sampled. |
| Table 9-54 | 0x0061 | 8 | R | 0 | Contains the early DMA enable bits to receive and transmit. |
| Table 9-55 | 0x0062 | 5 | RW | 0 | Controls the size of the selected transmit endpoint FIFO. |
| Table 9-56 | 0x0063 | 5 | RW | 0 | Controls the size of the selected receive endpoint FIFO. |
| Table 9-57 | 0x0064 | 14 | RW | 0 | Controls the start address of the selected transmit endpoint FIFO. |
| Table 9-59 | 0x0066 | 14 | RW | 0 | Controls the start address of the selected receive endpoint FIFO. |
| Table 9-60 | 0x0068 | 4 | W (VControl) | 0 | VControl is optionally a UTMI+ PHY vendor
register. UTMI+ specification defines a 4-bit VControl register. The latency for the write (as measured between the positive edge of the CLK at the end of the AHB write cycle and the positive edge of XCLK when the UTMI+ PHY VControl register is loaded) is between Hc + 3Xc and Hc + 4Xc, where Hc is a cycle of CLK and Xc is a cycle of XCLK. The minimum period between successive writes to the VControl register must be Hc + 4Xc to ensure that the value is not corrupted while it is being synchronized to the XCLK domain. |
| Table 9-61 | 0x0068 | 8 | R (VStatus) | VStatus is optionally a UTMI+ PHY vendor
register. UTMI+ specification defines an 8-bit VStatus register. The VSTATUS input bus is sampled once every six XCLK cycles. The latency between the VSTATUS input bus from the PHY changing and the new value being read from the VStatus register (measured to the positive edge of CLK at the end of the AHB read cycle) is between 2Hc + Xc and 3Hc + 6Xc, where Hc is a cycle of CLK and Xc is a cycle of XCLK. | |
| Table 9-62 | 0x006C | 16 | R | Returns information about the version of the USB controller. Specifically, the version of design (RTL) used to implement the USB controller. Useful for debug purposes. | |
| Reserved | 0x006E | N/A |