9.3.5 Common Registers
This section covers all registers in this category along with the address offset, functionality, and per bit details.
| Register Name | Address | Width | R/W Type | Reset Value | Description | |
|---|---|---|---|---|---|---|
| FADDR_REG Bit Definitions (Table 9-10) | 0x40043000 | 8 | RW | 0 | Write with the 7-bit address of the peripheral part of the transaction. This register applies to operations when the USB controller is used in peripheral mode only. It is ignored in Host mode. | |
| POWER_REG Bit Definitions (Table 9-11) | 0x40043001 | 8 | R | 0x20 | Controls suspend and resume signaling and some other basic operational aspects of the USB controller. | |
| TX_IRQ_REG Bit Definitions (Table 9-12) | 0x40043002 | 16 | R | 0 | Indicates which interrupts are active for endpoint 0 and transmit endpoints EP1, EP2, EP3, and EP4. These are the lowest 5 bits of the register. Interrupts are cleared when this register is read. | |
| RX_IRQ_REG Bit Definitions (Table 9-13) | 0x40043004 | 16 | R | 0 | Indicates which interrupts are active for receive endpoints EP1, EP2, EP3, and EP4. These are bits 1, 2, 3, and 4 of the register. Interrupts are cleared when this register is read. | |
| TX_IRQ_EN_REG Bit Definitions (Table 9-14) | 0x40043006 | 16 | RW | 0x1F | Provides interrupt enables for interrupts in TX_IRQ_REG. The endpoint0 and EP1, EP2, EP3, and EP4 have corresponding enable bits from bit 0 to bit 4 of this register. A value of 1 indicates that the interrupt is enabled. | |
| RX_IRQ_EN_REG Bit Definitions (Table 9-15) | 0x40043008 | 16 | 0x1E | Provides interrupt enables for interrupts in RX_IRQ_REG. The endpoints EP1, EP2, EP3, and EP4 have corresponding enable bits from bit 1 to bit 4 of this register. A value of 1 indicates that the interrupt is enabled. | ||
| USB_IRQ_REG Bit Definitions (Table 9-16) | 0x4004300A | 8 | R | 0 | Indicates that the status of USB interrupts. All active interrupts are cleared when the register is read. | |
| USB_IRQ_EN_REG Bit Definitions (Table 9-17) | 0x4004300B | 8 | RW | 0x06 | Provides interrupt enables for interrupts in USB_IRQ_REG. A value of 1 indicates that the interrupt is enabled. | |
| FRAME_REG Bit Definitions (Table 9-18) | 0x4004300C | 16 | R | 9 | Holds the last received frame number. This is an 11-bit number. | |
| INDEX_REG Bit Definitions (Table 9-19) | 0x4004300E | 4 | RW | 0 | Indicates which endpoint control and status registers are currently accessed from among the implemented transmit and receive endpoints (EP0, EP1, EP2, EP3, and EP4). Each transmit endpoint and each receive endpoint has its own set of control/status registers located between 0x40043100 and 0x400431FF addresses. In addition, one set of TX control/status and one set of RX control/status registers appear at 10h to 19h. Before accessing an endpoint’s control/status registers at 10h to 19h, the endpoint number should be written to the Index register to ensure that the correct control/status registers appear in the memory map. | |
| TEST_MODE_REG Bit Definitions (Table 9-20) | 0x4004300F | 8 | RW | 0 | Puts the USB controller in one of the four test modes for high speed operation described in the USB 2.0 specification. This register is not used in normal operation. | |