48.1 Revision History

Revision K - March 2025


Section	Description
Ordering Information	Updated the Diagram to reflect the addition of OTP
SYSCTRL	Added a note to the BOD33RDY bitfield in the PCLKSR Register Removed obsolete content from the ONDEMAND bitfield in the DFLLCTRL Register
USB	Corrected verbiage in the Register description for the EPINTENSETn Register
Electrical Characteristics at 85°C	Updated the Min and Typ Characteristics for table 37-52 in DFLL48M Characteristics
Electrical Characteristics at 105°C	Updated the Min and Typ Characteristics for table 38-25 in DFLL48M Characteristics
Electrical Characteristics at 125°C	Updated the Min and Typ Characteristics for table 39-37 and 39-38 in DFLL48M Characteristics Updated the Min and Max Characteristics for table 39-42 in OSC32K Characteristics
AEC-Q100 125°C Specifications	Updated the Min, Typ, and Max Characteristics for table 40-49 in DFLL48M Characteristics
Schematic Checklist	Updated Table 45-5 with a new MHz rating in Crystal Oscillator

Revision J - December 2024

Internal engineering updates. Non-public release.

Revision H - September 2021


Section	Description
SYSCTRL	Removed erroneous text from the DFLLRDY bitfield of the PCLKSR Register.
DMAC	Removed non-applicable text from Burst Transfer in DMA.
TCC	Updated the number of TCC Instances in Overview.
ADC	Updated the Equations in Prescaler for Single-Shot and Free-Running Modes.
AC	Added a new paragraph to Overview for L-Variant devices.
DAC	Updated Synchronization to reflect that no bits need synchronization.
Electrical Characteristics at 85°C	Updated the POR Operating Principle figure to properly reflect an Internal RESET in Power-On-Reset (POR) Characteristics Updated the following figures in BOD33 to properly display the Internal RESET: BOD33 Hysteresis OFF BOD33 Hysteresis ON Removed erroneous SS line from the SPI Timing Requirements in Host Mode figure in SERCOM in SPI Mode Timing
SAM DA1 Electrical Characteristics at 105°C	Updated the values in the BOD33 LEVEL Value table in BOD33.
Appendix B	Updated Ordering Information with a new table reflecting all ISELED parts.
Packaging Information	Updated the following packages with a new note: 64-Pin VQFN 48-Pin VQFN Added the following package: 64-Lead VQFN

Revision G - April 2021

This revision includes the updates as listed in the following table, and numerous typographical corrections throughout the document.


Section	Description
General	The SPI, I²S, and I²C standards use the terminology "Master" and "Slave". The equivalent Microchip terminology used in this document is "Host" and "Client" respectively. These terms have been updated throughout this document for this revision.
Features	Updated RWW to RWWEE for Memories
Ordering Information	Updated RWW to RWWEE in the Device Variant description
Pinout	Updated the following Pinouts to accurately display the RESET pin QFN48 QFN32 / TQFP32 UFBGA64 WLCSP45 WLCSP35
I/O Multiplexing	Added a new notes to table 7-1 for SERCOM and TCC3 availability Added a new note to table 7-2 for TCC3 availability Removed erroneous text from the header of Table 7-5 in SERCOM I²C Pins
Product Mapping	Updated RWW to RWWEE in the figure
Memories	Updated EEPROM and RWWEE text in Embedded Memories Updated RWW to RWWEE in all the tables in Physical Memory Map Updated Table 10-7 in NVM User Row Mapping to display text for Emulation
Processor and Architecture	Updated the Addresses of the bits in SRAM Quality of Service Updated the following registers, changing clear to set: PCA0 Register WPSET PCA1 Register WPSET PCA2 Register WPSET
DSU	Added verbiage for RWWEE Emulation to Chip Erase Updated table 13-3 in 32-bit Cyclic Redundancy Check CRC32 with proper capitalization on Emulation Updated table 13-6 in System Services Availability when Accessed Externally and Device is Protected with the correct RWWEE verbiage Updated the DEVSEL bit of the DID Register with information for Device identification
Clock System	Updated Read Request with new verbiage for the READREQ.RCONT and READREQ.RREQ bits
GCLK	Updated the GENDIV Register with a new Register property, and added a new column for the Maximum Division Factor to the table for the DIV bit.
SYSCTRL	Updated the following registers: XOSC with new verbiage for the AMPGC and GAIN bits DFLLCTRL - removed erroneous RUNSTDBY bit
RTC	Updated the Overview with new verbiage for clock sources selectable through the GCLK.
DMAC	Updated the following registers: BASEADDR with new text for the bitfield BASEADDR WRBADDR with new text for the bitfield WRBADDR SRCADDR with new text for the bitfield SRCADDR DSTADDR with new text for the bitfield DSTADDR DESCADDR bitfield was updated for 64 bit alignment in the DESCADDR register
EIC	Updated the EXTINTx bit of the INTENCLR register to read “disables the external interrupt.”
NVMCTRL	Updated the Overview with new text for the EEPROM Emulation array Updated Memory Organization with new EEPROM Emulation verbiage Updated NVM User Configuration with new EEPROM Emulation verbiage Updated the following registers: PARAM The ADDR bit of the ADDR Register was updated with new verbiage The LOCK bit of the LOCK Register was updated with the correct reset value
EVSYS	Updated Features with new event user verbiage Updated the CHSTATUS Register with a new Reset value for the USRRDY bitfield
SERCOM I²C	Updated the Signal Description with a cross reference to the proper I/O Multiplexing table In DMA, Interrupts and Events, erroneous information referring to the TX FIFO and RX FIFO was removed from table 28-1 and table 28-2 In Interrupts erroneous information regarding the RX FIFO and TX FIFO was removed Updated the SYNCBUSY Register to remove the SYSOP bitfield Updated the DATA Register with a new register Property and added a note to the DATA Bitfield
I²S	Added new slotsize information to PDM Reception.
TC	Updated the RCONT bit of the READREQ Register with new verbiage for clearing and reading the RREQ and RCONT bits.
USB	Updated the SPEED Bitfield of the STATUS Register with the proper allocation of low-speed and full-speed mode.
ADC	Updated the Block Diagram to properly display INTVCC0/1, and updated the note Updated the Note for the REFSEL bit of the REFCTRL Register
DAC	Updated the CTRLB Register with a new note for the REFSEL bitfield.
Electrical Characteristics at 85°C	In Maximum Clock Frequencies, table 37-7 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 37-24 37-25 37-26 Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 37-32 37-34 37-35 Updated table 37-38 in Bandgap and Internal 1.0V Reference Characteristics with new symbol values
Electrical Characteristics at 105°C	In Maximum Clock Frequencies, table 38-4 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 38-10 38-11 38-12 Updated table 38-14 in Performance with the Hardware Offset and Gain Correction by applying the Conditions value to the whole column Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 38-15 38-16 38-17
Electrical Specifications at 125°C	In Maximum Clock Frequencies, table 39-4 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 39-13 39-14 39-15 39-16 39-17 39-18 Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 39-19 39-20 39-22 39-23
AEC-Q100 125°C Specifications	In Maximum Clock Frequencies, table 40-7 and 40-9 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 40-24 40-25 40-26 40-27 Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 40-30 40-32 40-33 Updated table 40-36 in Bandgap and Internal 1.0V Reference Characteristics with new symbol values
SAM DA1 Electrical Characteristics	In Maximum Clock Frequencies, table 41-6 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 41-23 41-24 41-25 Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 41-28 41-30 Updated table 41-32 in Bandgap and Internal 1.0V Reference Characteristics with new symbol values
Appendix B	Added a new Appendix for ISELED Specifications.
Packaging	The following packages were updated with new drawings: 64TQFP 64 pin QFN 64 Lead QFN with Sawn Wettable Flanks 64-ball UFBGA 48 pin TQFP 48 pin QFN 48 lead QFN with Sawn Wettable Flanks 45-ball WLCSP 32 pin TQFP 32 pin QFN 32 lead QFN with Sawn Wettable Flanks 35-ball WLCSP (Device Variant B) 35-ball WLCSP (Device Variant C) 35-ball WLCSP (Device Variant D)

Revision F - March 2020

This revision includes the updates as listed in the following table, and several typographical corrections throughout the document.


Section	Description
Appendix A	Added a new appendix SIL 2 Enabled Functional Safety Devices
Packaging Information	Added ‘35-ball WLCSP (Device variant D)’
DAC	Updated the INTENSET register, changed disable to enable for interrupts. Updated the SYNCRDY bit of the INTENSET Register. Added information about internal 1.0V buffered reference voltage.
ADC	Added information about internal 1.0V buffered reference voltage. Updated CALIB register description.
SAM DA1 Electrical Characteristics	Updated I²C Pins Characteristics in I²C Configuration in I²C Pins. Updated label for internal 1.1V Bandgap Reference Added information about internal 1.0V buffered reference voltage for ADC and DAC.
SERCOM I²C	Updated the SYSOP bit of the SYNCBUSY Register with the removal of erroneous text
SERCOM SPI	Updated DOPO description.
EIC	Note added for CONFIGn registers.
DMAC	Updatetd Sleep mode operation description.
SYSCTRL	Removed reference to BOD12 registers. Added ENABLE bit in the VREG register.
DSU	Related linked added in the DID register description.

Revision E - January 2020

This revision encompasses changes made to combine the SAM D21 Data Sheet with the SAM DA1 Data Sheet to improve readability and information access.


Section	Description
Block Diagram	Added arrow between PORT and AHB-APB BRIDGE B.
Pinout	Updated section titles
Product Mapping	Updated the diagram to show the Internal Flash.
PORT I/O Pin Controller	Corrected the WRCONFIG register to show the DRVSTR bit.
SERCOM	Under Clock Generation - Baud-Rate Generator, the table was updated with a new information and equations.
SERCOM USART	Information regarding FIFO was removed as it is not supported on this device The FIFOCLR bit was removed from the CTRLB register The FIFOSPACE and FIFOPTR registers were removed
SERCOM SPI	Information on FIFO was removed as it is not supported on this device The FIFOCLR bit was removed from the CTRLB register The FIFOSPACE and FIFOPTR registers were removed
SERCOM I²C	Information on FIFO was removed as it is not supported on this device The FIFOCLR bit was removed from the CTRLB Slave Register Bit fields RXFF and TXFE were removed from the INTENCLR, INTENSET, and INTFLAG Slave Registers The LENERR bit was removed from the STATUS Slave Register Registers FIFOSPACE and FIFOPTR were removed from the Slave Registers The FIFOCLR bit was removed from the CTRLB Master Register Bit fields, RXFF and TXFE, were removed from the INTENCLR, INTENSET, and INTFLAG Master Registers Registers FIFOSPACE and FIFOPTR were removed from the Master Registers
Timer Counter (TC)	In Counter Mode, Count32 was updated with new TC numbering The register summaries for 8-bit Mode, 16-bit Mode, and 32-bit Mode were updated to correctly display
TCC	FCTRLA and FCTRLB had their naming corrected In the WEXCTRL register the DTIEN bit had the numbering updated In the DRVCTRL register the numbering was updated for the INVENx, NRVx, and NREx bits In the EVCTRL register the numbering was updated for the MCEOx, MCEIx, TCEIx, and TCINVx Registers In the INTENCLR, INTENSET, and INTFLAG registers the numbering was updated for the MCx bit In the STATUS register the numbering was updated for the CMPx and FAULTx bits The PATT register was updated to properly display the PGVx and PGEx bits The PATTB register was updated to properly display the PGVBx and PGEBx bits
USB	Updated cross references.
ADC	Updated the MUXPOS Bit table in the INPUTCTRL register.
AC	Updated the STARTx bit numbering in the CTRLB register Updated the bit numbering for the COMPEIx, COMPEOx, and WINEOx bits in the EVCTRL register Updated the bit numbering for the WINx, and COMPx bits in the INTENCLR, INTENSET, and INTFLAG registers Updated the bit numbering for the WSTATEx and STATEx bits in the STATUSA register Updated the bit numbering for the READYx bit in the STATUSB register Updated the bit numbering for the WSTATEx and STATEx bits in the STATUSC register Updated the bit numbering for the WINTSELx and WENx bits in the WINCTRL register
SAM DA1 Electrical Characteristics	This section was migrated into this data sheet from the original SAM DA1 data sheet.
Schematic Checklist	Updated External Reset Circuit with changes to the diagram External Reset Circuit Schematic.
Packaging Information	Updated Package Markings with a new marking diagram.

Rev D - 9/2018


Configuration Summary	Updated to Add new packages for device variant D.
Product Mapping	Updated diagram.
RTC	Updated READREQ register tables.
DMAC	Updated Channel Control B Register tables.
EVSYS – Event System	Updated the Channel Register tables Updated the User Register tables
DAC	Updated the Block Diagram to display ADC Input.
Electrical Characteristics at 85°C	Updated Decoupling Requirements table .
Electrical Characteristics at 105°C
Electrical Characteristics at 125°C
AEC-Q100 Electrical Characteristics at 125°C
Packaging Information	Updated the WLSCP 45-Ball Package diagram.

Rev. C – 06/2018


Features	Added Qualification AEC-Q100 Grade 1 (-40C to 125C).
Ordering Information	Added: under Package Grade Z = -40 – 125C Matte Sn Plating AEC-Q100
Electrical Characteristics	Updated with new chapter for AEC-Q100 Specifications.
Packaging Information	Added QFN package drawings with wettable flanks.

Rev. B – 04/2018


General	This revision was updated to include the SAM D21EL and SAM D21GL Variant information, which was released separately in DS40001883A. The SAM D21EL/SAM D21GL Data Sheet (DS40001883A) is superseded by this revision (DS40001882B). IOBUS start addressed is added which was missing in previous revision (DS40001882A).
Electrical Characteristics	Clarified ESR information for VDDCORE capacitor Typo addressed for VDDIN capacitor value
DMA	RUNSTDBY not supported, typo addressed
AC	Continuous Mode SleepWalking figure is updated
ADC	Bandgap reference as input was omitted in previous version of the data sheet. It is added in this version.
Packaging Information	WLCSP package drawings updated Thermal characteristic for 45-ball WLCSP & 64-pin UFBGA is added

Rev. A – 01/2017


General	Template: Updated from Atmel to Microchip template. Document number: Changed from the Atmel 42181 to Microchip xxxxx. Document revision letter reset to A. ISBN number added.
Electrical Characteristics	Die Revision F final characterization added. Power Consumption: Added Standby typical numbers for Device Variant C / Die Revision F. Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added characterization data for Device Variant C / Die Revision F.
Errata	New errata added: B Device Variant A: Errata reverence 15625, 15683, 15753 added. Device Variant B: Errata reverence 15625, 15683, 15753 added. Device Variant C: Errata reverence 15625, 15683, 15753 added.
Electrical Characteristics at 125°C	Die Revision F final characterization is preliminary. Power Consumption: Added Standby typical numbers for Device Variant C / Die Revision F. Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added characterization data for Device Variant C / Die Revision F.