33.22.6 PMC Peripheral Clock Status Register 0

Name: PMC_PCSR0
Offset: 0x0018
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 PID31PID30PID29PID28PID27PID26PID25PID24 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 PID23PID22PID21PID20PID19PID18PID17PID16 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 PID15PID14PID13PID12PID11PID10PID9PID8 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 PID7PID6PID5PID4PID3PID2   
Access RRRRRR 
Reset 000000 

Bits 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral Clock x Status

PID2 to PID31 refer to identifiers as defined in section “Peripheral Identifiers”. Other peripherals status can be read in PMC_PCSR1.
ValueDescription
0

The corresponding peripheral clock is disabled.
1

The corresponding peripheral clock is enabled.