33.22.38 PMC Audio PLL Control Register 0
| Name: | PMC_AUDIO_PLL0 |
| Offset: | 0x014C |
| Reset: | 0x000000D0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DCO_GAIN[1:0] | DCO_FILTER[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| QDPMC[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ND[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PLLFLT[3:0] | RESETN | PMCEN | PADEN | PLLEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | |
Bits 29:28 – DCO_GAIN[1:0] Digitally Controlled Oscillator Gain Selection
For optimization, the value of this field must be configured to 0.
Bits 27:24 – DCO_FILTER[3:0] Digitally Controlled Oscillator Filter Selection
For optimization, the value of this field must be configured to 0.
Bits 22:16 – QDPMC[6:0] Output Divider Ratio for PMC Clock
fpmc = fref × ((ND + 1) + FRACR ÷ 222) / (QDPMC + 1)
Bits 14:8 – ND[6:0] Loop Divider Ratio
Bits 7:4 – PLLFLT[3:0] PLL Loop Filter Selection
Default value should be 13 (0xD).
Bit 3 – RESETN Audio PLL Reset
| Value | Description |
|---|---|
| 0 |
The audio PLL is in reset state. |
| 1 |
The audio PLL is in active state. |
Bit 2 – PMCEN PMC Clock Enable
| Value | Description |
|---|---|
| 0 |
The output clock of the audio PLL is not sent to the PMC. |
| 1 |
The output clock of the audio PLL is sent to the PMC. |
Bit 1 – PADEN Pad Clock Enable
| Value | Description |
|---|---|
| 0 |
The external audio pin CLK_AUDIO is driven low. |
| 1 |
The external audio pin CLK_AUDIO is driven by AUDIOPINCLK. |
Bit 0 – PLLEN PLL Enable
| Value | Description |
|---|---|
| 0 |
The Audio PLL is disabled. |
| 1 |
The Audio PLL is enabled |