14.8.10 RX_CTRL
| Name: | RX_CTRL |
| Offset: | 0x0A |
| Reset: | 0x17 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| JCM_EN | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
Bit 5 – JCM_EN JCM_EN
The register bit JCM_EN controls digital clock jitter module.
| Value | Description |
|---|---|
| 0x0 | Digital clock jitter module is disabled. |
| 0x1 | Digital clock jitter module is enabled. |
- If the Antenna Diversity algorithm is enabled (ANT_DIV_EN = 1), the value shall be set to PDT_THRES = 3, otherwise it shall be set back to the reset value. This is not automatically done by the hardware.