14.8.6 PHY_RSSI

The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and a RSSI value.

Name:	PHY_RSSI
Offset:	0x06
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	RX_CRC_VALID	RND_VALUE[1:0]		RSSI[4:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – RX_CRC_VALID RX_CRC_VALID

The register bit RX_CRC_VALID signals the FCS check status for a received frame.

Table 14-57. RX_CRC_VALID
Value	Description
0x0	FCS is not valid
0x1	FCS is valid

Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt is issued, caused by a new frame reception.

Bits 6:5 – RND_VALUE[1:0] RND_VALUE

The 2-bit random value can be retrieved by reading register bits RND_VALUE.

Table 14-55. RND_VALUE
Value	Description
0x0	Deliver two bit noise value within receive state. Valid values are [3, 2, …, 0].

The radio transceiver shall be in Basic Operating Mode receive state.

Bits 4:0 – RSSI[4:0] RSSI

Received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3.1dB.

Table 14-56. RSSI
Value	Description
0x00	Minimum RSSI value
0x1C	Maximum RSSI value

The result of the automated RSSI measurement is stored in the RSSI bits in the PHY_RSSI register. The value is updated every t_RSSI = 2μs in any receive state.

The result of the automated RSSI measurement is stored in register bits RSSI (register 0x06, PHY_RSSI). The value is updated at time intervals according to the RSSI Update Interval table in any receive state. RSSI is a number between zero and 28, representing the received signal strength.