14.8.23 XAH_CTRL_1

The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode.

Name: XAH_CTRL_1
Offset: 0x17
Reset: 0x00
Property: -

Bit 76543210 
 CSMA_LBT_MODEAACK_FLTR_RES_FTAACK_UPLD_RES_FTAACK_ACK_TIMEAACK_PROM_MODE 
Access R/WR/WR/WR/WRR/WR/WR 
Reset 00000000 

Bit 6 – CSMA_LBT_MODE CSMA_LBT_MODE

The register bit CSMA_LBT_MODE switched between CSMA-CA or Listen Before Talk (LBT) algorithm within TX_ARET mode.

Table 14-102. CSMA_LBT_MODE
Value Description
0x0 CSMA-CA alogrithm is used.
0x01 LBT algorithm is used

If set to zero (default), CSMA-CA algorithm is used during TX_ARET for clear channel assessment. Otherwise, the LBT specific listening mode is applied.

Bit 5 – AACK_FLTR_RES_FT AACK_FLTR_RES_FT

Filter reserved frame types like data frame type. The register bit AACK_FLTR_RES_FT shall only be set if register bit AACK_UPLD_RES_FT = 1.

Table 14-97. AACK_FLTR_RES_FT
Value Description
0x0(1) Filtering reserved frame types is disabled
0x1(2) Filtering reserved frame types is enabled
  1. If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked for a valid FCS.
  2. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE 802.15.4–2006.

Reserved frame types are explained in IEEE 802.15.4 Section 7.2.1.1.1.

Bit 4 – AACK_UPLD_RES_FT AACK_UPLD_RES_FT

Upload reserved frame types within RX_AACK mode.

Table 14-98. AACK_UPLD_RES_FT
Value Description
0x0 Upload of reserved frame types is disabled
0x1(1) Upload of reserved frame types is enabled
  1. If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are further processed. For those frames, an IRQ_3 (TRX_END) interrupt is generated if the FCS is valid.

In conjunction with the configuration bit AACK_FLTR_RES_FT, these frames are handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An IRQ_5 (AMI) interrupt is issued, if the addresses in the received frame match the node’s addresses.

That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and transmitted if it was requested by the received frame. If this is not wanted register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set.

Bit 2 – AACK_ACK_TIME AACK_ACK_TIME

The register bit AACK_ACK_TIME controls the acknowledgment frame response time within RX_AACK mode.

Table 14-99. AACK_ACK_TIME
Value Description
0x0 Acknowledgment time is 12 symbol periods (a Turnaround Time)
0x1

Two symbol periods: BPSK-20, OQPSK-{100,200,400};

Three symbol periods: BPSK-40, OQPSK-{250,500,1000}

According to IEEE 802.15.4-2006, Section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK_ACK_TIME.

Alternatively, if AACK_ACK_TIME = 1, the acknowledgment response time is reduced according to the table below.

Table 14-100. Short ACK Response Time (AACK_ACK_TIME=1)
PHY Mode ACK Response Time [symbol periods]
BPSK-20, OQPSK-{100,200,400} 2
BPSK-40, OQPSK-{250,500,1000} 3

The reduced ACK response time is particularly useful for the High Data Rate Modes.

Bit 1 – AACK_PROM_MODE AACK_PROM_MODE

The register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode.

Table 14-101. AACK_PROM_MODE
Value Description
0x0 Promiscuous mode is disabled
0x1 Promiscuous mode is enabled

Refer to [2] IEEE 802.15.4-2006 Section 7.5.6.5.

If this register bit is set, every incoming frame with a valid PHR finishes with IRQ_3 (TRX_END) interrupt even if the third level filter rules do not match or the FCS is not valid. However, register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set accordingly.

In contrast to [2] IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or use Basic Operating Mode instead.