14.8.21 RX_SYN
The register RX_SYN controls the blocking of receiver path and the sensitivity threshold of the receiver.
| Name: | RX_SYN |
| Offset: | 0x15 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RX_PDT_DIS | RX_OVERRIDE[2:0] | RX_PDT_LEVEL[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – RX_PDT_DIS RX_PDT_DIS
The register bit RX_PDT_DIS prevents the reception of a frame during RX phase.
| Value | Description |
|---|---|
| 0x0 | RX path is enabled |
| 0x1 | RX path is disabled |
RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes. An ongoing frame reception is not affected. This operation mode is independent of the setting of register bits RX_PDT_LEVEL.
Bits 6:4 – RX_OVERRIDE[2:0] RX_OVERRIDE
The register bits RX_OVERRIDE control the RXO functions during RX phase. During the receive process the validity of the current frame and the occurrence of a strong interferer is checked continuously. In either of those cases the reception is automatically restarted to increase the overall system availability and throughput with respect to correct received packets.
| Value | Description |
|---|---|
| 0x0(1) | All RX override functions are disabled (default) |
| 0x6(2) |
IPAN scanning is enabled, 9dB Energy Detection (ED) check is enabled, Link Quality (LQ) check is enabled |
| Reserved | All other values are reserved |
- Frames are decoded up to the length specified in the PHR field, independent of any interference while receiving this frame.
- Detection of strong interference while receiving a frame (where the frame is destroyed anyway) and fast re-synchronization to a potential new frame.
- There is no TRX_END interrupt for an ongoing frame reception when re-synchronization is forced by strong interference.
The Receiver Override can be used without performance degradation in combination with any modulation scheme and data rate.
Bits 3:0 – RX_PDT_LEVEL[3:0] RX_PDT_LEVEL
The register bits RX_PDT_LEVEL desensitize the receiver in steps of 3dB.
| Value | Description |
|---|---|
| 0x00 |
Maximum RX sensitivity |
| 0x0F |
RX input level[dBm] > RSSI_BASE_VAL[dBm] + 3[dB] x 14 |
These register bits desensitize the receiver such that frames with an RSSI level below the RX_PDT_LEVEL threshold level (if RX_PDT_LEVEL > 0) are not received. For a RX_PDT_LEVEL > 0 value the threshold level can be calculated according to the following formula:
PRF[dBm] > RSSIBASE_VAL[dBm] + 3[dB] x (RX_PDT_LEVEL - 1)
If register bits RX_PDT_LEVEL = 0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength.
If register bits RX_PDT_LEVEL > 0, the current consumption of the receiver in all RX listening states is reduced by 500μA.