1.2.7.1 IP Cores for ADC Data Processing and Sequence Control

Enables all the Analog Block features: sequencing, flag generation, data averaging, and general ADC management. You can enable or disable access to ADC results, ADC Status ASSC RAM, SMEV RAM, SMEV Status, ACM Bus, and ACM Clock.

ASSC is responsible for setting the sample order in the ADC and SMEV evaluates the converted analog data. This option instantiates the Analog Block and the complete Analog System Controller (includes ASSC RAM, SMEV RAM, and SMTR RAM), as shown in the figure below.

Figure 1-9. System Diagram for IP Cores and ADC Data Processing and Sequence Control Options

This option generates the following files:

ACM MEM files
ASSC IP, ASSC RAM, ASSC Wrappers, & ASSC MEM files
SMEV IP, SMEV RAM, SMEV Wrappers & SMEV MEM files
SMTR IP, SMTR RAM, SMTR Wrappers & SMTR MEM files

Enabling user access to ADC results, ADC status, ASSC RAM, SMEV RAM, and SMEV Status exposes additional interfaces and ports. See the help topics associated with each option for more information.