2.2.11.2 ADC Clock Calculation

The ADC clock period is calculated as:

ADC Clock Period = (4 × (1 + Clock Divider Setting)) / System Clock Period

The ADC Clock period has a maximum possible frequency of 10MHz.

ASB automatically computes values for the sample time control (STC), clock divider setting (TVC), and ADC Clock Period based on your sample time requirement. Only certain divider factors exist to create the ADC Clock; because of the divider factors and peripherals' acquisition times, certain system frequencies result in a faster ADC Clock.

The goal of ASB is to meet the specified acquisition and hold time requirements with the highest possible ADC Clock frequency, which implies a low TVC value and high STC value.

For a discussion of the clocks involved in an Analog System design, see the Designing with Analog System Builder section.