2.1.7.1 IP Cores for ADC data processing and sequence control

This configuration enables the full Analog System feature set, including sequencing, flag generation, data averaging, and general ADC management. This option allows you to enable or disable user access to ADC results, ADC Status ASSC RAM, SMEV RAM, SMEV Status, ACM Bus, and ACM Clock.

The ASSC is responsible for setting the sample order in the ADC and SMEV evaluates the converted analog data. This option instantiates the Analog Block and the complete Analog System Controller (includes ASSC RAM, SMEV RAM, and SMTR RAM), as shown in the following figure.

Figure 2-7. System Diagram for IP Cores and ADC Data Processing and Sequence Control Options

Generated Files

Selecting this option generates the following files:

ACM MEM files
ASSC IP, ASSC RAM, ASSC Wrappers, and ASSC MEM files
SMEV IP, SMEV RAM, SMEV Wrappers and SMEV MEM files
SMTR IP, SMTR RAM, SMTR Wrappers and SMTR MEM files

Enabling user access to ADC results, ADC status, ASSC RAM, SMEV RAM, and SMEV status exposes additional interfaces and ports. For more information about each option, see the corresponding help topics.