2.1.7.2 IP Cores for ADC Sequence control

This configuration instantiates only the analog block model and the ASSC RAM. The data processing portions of the controller (SMEV and SMTR) are omitted from the design (as shown in the figure below). If you select this option, you must process the ADC data directly from the ADC RESULT bus or the ASSC RAM.

Figure 2-8. System Diagram for IP Cores for ADC Sequence Control Only

This configuration disables the following functionality:

Flag generation for peripherals (peripheral flag grid).
Data averaging (Digital Filtering Factor and Initial Averaging Value).
SMEV RAM access.
The ability to specify an external resistor for the Current Monitor.

Note: You must explicitly enable access to the ADC result and/or ASSC RAM data interfaces to read ADC data.

Generated Files

Selecting this option generates the following files:

ACM MEM files
ASSC IP, ASSC RAM, ASSC Wrappers, and ASSC MEM files