Clock constraints enable you to specify your clock sources and clock requirements, such as the
frequency and duty cycle. SmartTime detects possible clocks by tracing back the design from
the clock pins of all sequential components until it finds an input port, the output of
another sequential element, or the output of a PLL. SmartTime classifies clock sources into
three types:
Grouping clocks into these three types helps you manage clock domains efficiently when you add a
new clock domain for analysis or when you create a new clock constraint using the Select
Source Pins for Clock Constraint dialog box (as shown in the following figure).Figure 21-25. Select Source Pins for Clock Constraint Dialog Box
