Explicit clocks are pins or ports connected to the clock pin of one or more sequential component,
and where each clock is one of the following:
The output of a PLL
An input port that does not get gated
between the source and the clock pins it drives
The output pin of a sequential element
that does not get gated between the source and the clock pins it drives
Any pin or port on which a clock
constraint was specified
By default, SmartTime displays domains with explicit clocks in the Timing Analysis View. You can
browse these domains in the Domain Browser of the Timing Analysis View.Figure 21-26. Explicit Clocks
