1.2.9.2 IP Cores for ADC Sequence Control with Calibration

Figure 1-13. System Diagram for IP Cores for ADC Sequence Control Only

This configuration instantiates only the analog block model and the ASSC RAM. The data processing portions of the controller (SMEV and SMTR) are omitted from the design (as shown in the figure below). If you select this option, you must process the ADC data directly from the ADC RESULT bus or the ASSC RAM.