1.2.9.1 IP Cores for ADC Data Processing and Sequence Control with Calibration
Figure 1-12. System Diagram for IP Cores and ADC Data Processing and Sequence Control
OptionsEnables all the Analog Block features: sequencing, flag generation, data averaging, and
general ADC management. You can enable or disable access to ADC results, ADC Status ASSC RAM,
SMEV RAM, SMEV Status, ACM Bus, and ACM Clock.
