You drive this port during active and idle modes to lower static Icc. When driving this pin, you must deselect the SRAM/FIFO for some determined time (counter value) or for a particular condition in your logic. This port has no effect if the port BLK is de-asserted (BLK port is active low), that is if BLK is high, then the LP port value is irrelevant.
FF (Flash*Freeze) Port (Active Low)
Connect this port directly to your Flash*Freeze pin (INBUF_FF output) in Flash*Freeze Type 1. It must be inverted when driven by housekeeping logic involving the ULSICC macro in Flash*Freeze Type 2. Connect this port directly to the Flash_Freeze_Enabled port of the Flash*Freeze Management IP if you are using it to implement Flash*Freeze Type 2. Asserting this port ensures that the SRAM/FIFO does not stay in WRITE and/or READ mode when the device enters Flash*Freeze mode.
