2.1.23.4 ADC Clock

The ADC clock is generated internally within the analog block (AB). It is configured automatically by the ASB and is not exposed as a user‑controlled clock.

The maximum achievable ADC clock frequency is determined by the FASTCLK value entered in the ASB during analog system configuration and by the acquisition times specified for each peripheral.

Only a limited set of divider values is available in the AB macro for ADC clock generation (for example, 0, 4, 8, 12, 16, and so on). As a result, certain system clock frequencies allow higher ADC clock rates than others.

For example, a system clock frequency of 40 MHz allows a maximum ADC clock of 10 MHz, whereas a system clock frequency of 50 MHz results in a lower maximum ADC clock frequency.