3.10.7.4.1.1 T3CR – Timer3 Control Register


Bit	7	6	5	4	3	2	1	0
	T3ENA	T3TOS	T3RES	T3TOP	T3CPRM	T4CRM	T3CTM	T3OTM
Access	R/W	R/W	W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – T3ENA Timer3 Enable

This bit controls the Timer3 block. The T3ENA bit must be written to logic ‘1’ to enable Timer3. If the T3ENA bit is written to logic ‘0’, Timer3 is disabled. Reading this bit shows the actual state of Timer3. Because internal synchronization requires 2½ asynchronous CL3 clock cycles to enable or disable Timer3, it may take some time to read a logic ‘1’ after having enabled Timer3. The same applies for disabling.

Bit 6 – T3TOS Timer3 Toggle with Start

The T3TOS bit must be written to logic ‘1’ if the modulator output of Timer3 must toggle when the timer is enabled with T3ENA. If the T3TOS bit is written to logic ‘0’, the modulator output of Timer3 is not toggled on timer enable.

Bit 5 – T3RES Timer3 Reset

The T3RES bit can be written to logic ‘1’ to reset the prescaler and counter. This is only allowed if the timer is stopped (T3ENA = 0). The T3RES bit is automatically cleared one cycle after the write.

Bit 4 – T3TOP T3 Toggle Output Preset

The T3TOP bit must be written to logic ‘1’ to set the toggle flip-flop. If the T3TOP bit is written to logic ‘0’, it resets the toggle flip-flop. This bit allows the programmer to preset the toggle output flip-flop in the modulator of Timer3.

Note: If T3ENA = 1, no output preset is possible.

Bit 3 – T3CPRM Timer3 Capture Reset Mask

The T3CRM bit must be written to logic ‘1’ to enable the counter reset if a match of the counter with the compare register (T3COR) occurs. If the T3CRM bit is written to logic ‘0’, the counter reset is disabled.

Bit 2 – T4CRM Timer4 Compare Reset Mask

The T4CRM bit must be written to logic ‘1’ to enable the counter reset if a match of the counter with the compare register (T4COR) occurs. If the T4CRM bit is written to logic ‘0’, the counter reset is disabled.

Bit 1 – T3CTM Timer3 Compare Toggle Mask

The T3CTM bit must be written to logic ‘1’ to enable the compare toggle. A match of the counter with the compare register (T3COR) toggles the output flip-flop in the modulator of Timer3. If the T3CTM bit is written to logic ‘0’, the compare toggle is disabled.

Bit 0 – T3OTM Timer3 Overflow Toggle Mask

The T3OTM bit must be written to logic ‘1’ to enable the overflow toggle. A counter overflow generates an output clock of the counter (CLK_T3). If the T3OTM bit is written to logic ‘0’, the overflow toggle is disabled.

Name:	T3CR
Offset:	0x013
Reset:	0x00