3.10.7.4.1.5 T3IMR – Timer 3
Interrupt Mask Register
| Name: | T3IMR |
| Offset: | 0x07F |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | T3CPIM | T3CIM | T3OIM | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – T3CPIM Timer3 Capture
Interrupt Mask
If this bit is written to
‘1’, and the I flag in SREG is set (interrupts globally
enabled), the Timer3 input capture interrupt is enabled. The corresponding interrupt
vector is executed when the T3ICF flag, located in T3IFR, is
set.
Bit 1 – T3CIM Timer3 Compare
Interrupt Mask
If the T3CIM bit is written to
‘1’ and the I bit in SREG is set, the Timer3 compare match
interrupt is enabled. The corresponding interrupt is executed if a compare match in
Timer3 occurs and when the T3COF bit is set in the Timer3 interrupt flag register
(T3IFR).
Bit 0 – T3OIM Timer3 Overflow
Interrupt Mask
If the T3OIM bit is written to
‘1’ and the I bit in SREG is set, the Timer3 overflow interrupt
is enabled. The corresponding interrupt is executed if an overflow in Timer3 occurs
and when the T3OFF bit is set in the Timer3 interrupt flag register
(T3IFR).
