3.10.7.4.1.10 T3CNTH – Timer3
Counter Register High Byte
The counter register (T3CNTH) contains the upper 8-bit of the counter value. It must
be read only when the timer is disabled (T3CR.T3ENA = 0). Due to
the asynchronous implementation it can result in unpredictable read values if
ignored.
Name:
T3CNTH
Offset:
0x078
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
T3CNTH[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – T3CNTH[7:0] Timer3 Counter
Value High Byte
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