3.10.7.4.1.4 T3IFR – Timer3
Interrupt Flag Register
| Name: | T3IFR |
| Offset: | 0x017 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | T3ICF | T3COF | T3OFF | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – T3ICF Timer3 Input
Capture Flag
This flag is set when a
capture event occurs on the selected capture source and indicates that the counter
value was transferred to the capture register (T3ICR). If the I bit in SREG and the
T3CPIM bit in the T3IMR register are set, the MCU jumps to the corresponding
interrupt vector. T3ICF is automatically cleared when the interrupt routine is
executed. Alternatively, T3ICF can be cleared by writing a logic
‘1’ to this bit location.
Bit 1 – T3COF Timer3 Compare
Flag
This flag is set during the
clock cycle after the Timer3 counter value has matched with the compare register. If
the I bit in SREG and the T3CIM bit in the T3IMR register are set, the MCU jumps to
the corresponding interrupt vector. The flag (T3COF) is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical
‘1’ to it.
Bit 0 – T3OFF Timer3 Overflow
Flag
This flag is set by the T3OVF
signal when the counter reaches its maximum value (0xFFFF). If the I bit in SREG and
the T3OIM bit in the T3IMR register are set, the MCU jumps to the corresponding
interrupt vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical ‘1’ to
it.
