3.10.7.4.1.3 T3MRB – Timer3
Mode Register B
| Name: | T3MRB |
| Offset: | 0x07E |
| Reset: | 0x00 |
This register must
be modified only while the timer is disabled (T3CR.T3ENA = 0).
Modifying the bits during operation leads to unpredictable
operation.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | T3ICS[2:0] | T3CE[1:0] | T3CNC | T3SCE | | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:5 – T3ICS[2:0] Timer3 Input
Capture Select
The T3ICS[2:0] bits select the
input capture signal of Timer3 as shown in the following table.
Table 3-96. Timer3 Input Capture
Signal Select Bit Description| T3ICS[2:0] | Description |
|---|
0 | 0 | 0 | CLKT2 |
0 | 0 | 1 | TRPA |
0 | 1 | 0 | TRPB |
0 | 1 | 1 | TICP |
1 | 0 | 0 | CLKSRC |
1 | 0 | 1 | Reserved (CLKSRC) |
1 | 1 | 0 | Reserved (CLKSRC) |
1 | 1 | 1 | Reserved (CLKSRC) |
Bits 4:3 – T3CE[1:0] Timer3 Capture Edge
Select
The T3CE1 and T3CE0 bits
select the edge from all input signals of Timer3 as shown in the following table.
Table 3-97. Timer3 Capture Edge
Select Bit Description| T3CE[1:0] | Input Capture Edge Signal of Timer3 |
|---|
0 | 0 | Disable edge detect |
0 | 1 | Rising edge |
1 | 0 | Falling edge |
1 | 1 | Both edges |
Bit 2 – T3CNC Timer3 Input
Capture Noise Canceller
Setting this bit to
‘1’ activates the input capture noise canceller. When the noise
canceller is activated, the input from the input capture pin is filtered. To change
its output, the filter function requires four successive samples of the input
capture pin of equal value. The input capture is, therefore, delayed by four counter
clock (CL3) cycles when the noise canceller is enabled.
Bit 1 – T3SCE Timer3 Software
Capture Enable
The T3SCE bit must be written
to logic ‘1’ to enable a software capture event. The T3SCE bit is
cleared after the counter value is saved in the capture register. The Timer3 counter
value is readable via its capture register while it is
running.
Bit 0 – Reserved Bit
This bit is reserved and read
as ‘0’.
