3.10.7.4.1.2 T3MRA – Timer3
Mode Register A
| Name: | T3MRA |
| Offset: | 0x07D |
| Reset: | 0x00 |
This register must
be modified only while the timer is disabled (T3CR.T3ENA = 0).
Modifying the bits during operation leads to unpredictable
operation.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | T3PS[2:0] | T3CS[1:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bits 4:2 – T3PS[2:0] Timer3 Prescaler
Select
The T3PS[2:0] bits select the
prescaler values of Timer3 as shown in the following table.
Table 3-94. Timer3 Prescaler Value
Select Bit Description| T3PS[2:0] | Prescaler Value |
|---|
0 | 0 | 0 | 1 |
0 | 0 | 1 | 2 |
0 | 1 | 0 | 4 |
0 | 1 | 1 | 8 |
1 | 0 | 0 | 16 |
1 | 0 | 1 | 32 |
1 | 1 | 0 | 64 |
1 | 1 | 1 | Reserved |
Bits 1:0 – T3CS[1:0] Timer 3 Clock
Select
The T3CS[1:0] bits select the
input clock (CL3) of Timer3 as shown in the following table.
Table 3-95. Timer3 Input Clock
Select Bit Description| T3CS[1:0] | Input Clock (CL3) of the Prescaler |
|---|
0 | 0 | CLKFRC |
0 | 1 | CLKT |
1 | 0 | CLKXTO4 |
1 | 1 | CLKXTO2 |
