35.7.43 Tx Buffer Configuration

Table 35-61. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	TXBC
Offset:	0x1C0
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
		TFQM	TFQS[5:0]
Access		RW	RW	RW	RW	RW	RW	RW
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
			NDTB[5:0]
Access			RW	RW	RW	RW	RW	RW
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TBSA[13:6]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TBSA[5:0]
Access	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0

Bit 30 – TFQM Tx FIFO/Queue Mode

Bits 29:24 – TFQS[5:0] Transmit FIFO/Queue Size

Bits 21:16 – NDTB[5:0] Number of Dedicated Transmit Buffers

Bits 15:2 – TBSA[13:0] Tx Buffers Start Address

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