35.7.19 Timeout Counter Configuration

This register is write-restricted and writable if both CCCR.CCE bit (CCCR <1>) and CCCR.INIT bit (CCCR <0>) are set.

Table 35-37. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	TOCC
Offset:	0x128
Reset:	0xFFFF0000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	TOP[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	1	1	1	1	1	1	1	1


Bit	23	22	21	20	19	18	17	16
	TOP[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	1	1	1	1	1	1	1	1


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
						TOS[1:0]		ETOC
Access						RW	RW	RW
Reset						0	0	0

Bits 31:16 – TOP[15:0] Timeout Period

Start value of the Timeout Counter (down-counter). Configures the Timeout Period.

Bits 2:1 – TOS[1:0] Timeout Select

When operating in Continuous mode, a write to TOCV register presets the counter to the value configured by bit TOCC.TOP (TOCC<31:16>) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by bit TOCC.TOP (TOCC<31:16>). Down-counting is started when the first FIFO element is stored.

Value	Name	Description
0	CONT	Continuout operation
1	TXEF	Timeout controlled by TX Event FIFO
2	RXF0	Timeout controlled by Rx FIFO 0
3	RXF1	Timeout controlled by Rx FIFO 1

Bit 0 – ETOC Enable Timeout Counter

Value	Description
0	Timeout Counter disabled.
1	Timeout Counter enabled.