35.7.5 Interrupt Flag Status and Clear register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x030 |
| Reset: | 0x00000000 |
| Property: | R/K |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BERR | DBG | ||||||||
| Access | R/HS/K | R/HS/K | |||||||
| Reset | 0 | 0 |
Bit 1 – BERR AHB Bus Error Detection
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will set the AHB Bus Error Detection Interrupt Flag.
| Value | Description |
|---|---|
| 0 | The AHB Bus Error Detection Flag is cleared. |
| 1 | The AHB Bus Error Detection Flag is set. |
Bit 0 – DBG Debug Message Reception
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will set the Debug Message Interrupt Flag.
| Value | Description |
|---|---|
| 0 | The Debug Message Flag is cleared. |
| 1 | The Debug Message Flag is set. |