35.7.47 Tx Buffer Add Request

Note: If an add request is applied for a Tx Buffer with pending transmission request (the corresponding TXBRP bit is already set), this add request is ignored.
Table 35-65. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: TXBAR
Offset: 0x1D0
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
 AR31AR30AR29AR28AR27AR26AR25AR24 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 2322212019181716 
 AR23AR22AR21AR20AR19AR18AR17AR16 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 15141312111098 
 AR15AR14AR13AR12AR11AR10AR9AR8 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 76543210 
 AR7AR6AR5AR4AR3AR2AR1AR0 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 

Bit 31 – AR31 Add Request 31

Bit 30 – AR30 Add Request 30

Bit 29 – AR29 Add Request 29

Bit 28 – AR28 Add Request 28

Bit 27 – AR27 Add Request 27

Bit 26 – AR26 Add Request 26

Bit 25 – AR25 Add Request 25

Bit 24 – AR24 Add Request 24

Bit 23 – AR23 Add Request 23

Bit 22 – AR22 Add Request 22

Bit 21 – AR21 Add Request 21

Bit 20 – AR20 Add Request 20

Bit 19 – AR19 Add Request 19

Bit 18 – AR18 Add Request 18

Bit 17 – AR17 Add Request 17

Bit 16 – AR16 Add Request 16

Bit 15 – AR15 Add Request 15

Bit 14 – AR14 Add Request 14

Bit 13 – AR13 Add Request 13

Bit 12 – AR12 Add Request 12

Bit 11 – AR11 Add Request 11

Bit 10 – AR10 Add Request 10

Bit 9 – AR9 Add Request 9

Bit 8 – AR8 Add Request 8

Bit 7 – AR7 Add Request 7

Bit 6 – AR6 Add Request 6

Bit 5 – AR5 Add Request 5

Bit 4 – AR4 Add Request 4

Bit 3 – AR3 Add Request 3

Bit 2 – AR2 Add Request 2

Bit 1 – AR1 Add Request 1

Bit 0 – AR0 Add Request 0