Note: If an add request is applied for a
Tx Buffer with pending transmission request (the corresponding TXBRP bit is already
set), this add request is ignored.
Table 35-65. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
TXBAR
Offset:
0x1D0
Reset:
0x00000000
Property:
RW
Bit
31
30
29
28
27
26
25
24
AR31
AR30
AR29
AR28
AR27
AR26
AR25
AR24
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
AR23
AR22
AR21
AR20
AR19
AR18
AR17
AR16
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
AR15
AR14
AR13
AR12
AR11
AR10
AR9
AR8
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit 31 – AR31 Add Request 31
Bit 30 – AR30 Add Request 30
Bit 29 – AR29 Add Request 29
Bit 28 – AR28 Add Request 28
Bit 27 – AR27 Add Request 27
Bit 26 – AR26 Add Request 26
Bit 25 – AR25 Add Request 25
Bit 24 – AR24 Add Request 24
Bit 23 – AR23 Add Request 23
Bit 22 – AR22 Add Request 22
Bit 21 – AR21 Add Request 21
Bit 20 – AR20 Add Request 20
Bit 19 – AR19 Add Request 19
Bit 18 – AR18 Add Request 18
Bit 17 – AR17 Add Request 17
Bit 16 – AR16 Add Request 16
Bit 15 – AR15 Add Request 15
Bit 14 – AR14 Add Request 14
Bit 13 – AR13 Add Request 13
Bit 12 – AR12 Add Request 12
Bit 11 – AR11 Add Request 11
Bit 10 – AR10 Add Request 10
Bit 9 – AR9 Add Request 9
Bit 8 – AR8 Add Request 8
Bit 7 – AR7 Add Request 7
Bit 6 – AR6 Add Request 6
Bit 5 – AR5 Add Request 5
Bit 4 – AR4 Add Request 4
Bit 3 – AR3 Add Request 3
Bit 2 – AR2 Add Request 2
Bit 1 – AR1 Add Request 1
Bit 0 – AR0 Add Request 0
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.