35.7.9 Core Release

Table 35-27. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CREL_MCAN
Offset:	0x100
Reset:	0x33000000
Property:	R


Bit	31	30	29	28	27	26	25	24
	REL[3:0]				STEP[3:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	1	1	0	0	1	1


Bit	23	22	21	20	19	18	17	16
	SUBSTEP[3:0]				YEAR[3:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MON[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DAY[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 31:28 – REL[3:0] Core Release

Bits 27:24 – STEP[3:0] Step of Core Release

Bits 23:20 – SUBSTEP[3:0] Sub-step of Core Release

Bits 19:16 – YEAR[3:0] Timestamp year

Bits 15:8 – MON[7:0] Timestamp month

Bits 7:0 – DAY[7:0] Timestamp day

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.