35.7.17 Timestamp Counter Configuration

This register is write-restricted and writable only if both CCCR.CCE bit (CCCR <1>) and CCCR.INIT bit (CCCR <0>) are set.
Table 35-35. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: TSCC
Offset: 0x120
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     TCP[3:0] 
Access RWRWRWRW 
Reset 0000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       TSS[1:0] 
Access RWRW 
Reset 00 

Bits 19:16 – TCP[3:0] Timestamp Counter Prescaler

ValueDescription
0x0 - 0xFConfigures the timestamp and timeout counters time unit in multiples of CAN bit times [1...16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Bits 1:0 – TSS[1:0] Timestamp Select

This field defines the timestamp counter selection.
ValueNameDescription
0ZEROTimestamp counter value always 0x0000
1INCTimestamp counter value incremented by TCP
2EXTExternal timestamp counter value used