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35.7.25 Interrupt Enable
Table 35-43. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: IE Offset: 0x154 Reset: 0x00000000 Property: RW
Bit 31 30 29 28 27 26 25 24 ARAE PEDE PEAE WDIE BOE EWE Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 EPE ELOE BEUE BECE DRXE TOOE MRAFE TSWE Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 TEFLE TEFFE TEFWE TEFNE TFEE TCFE TCE HPME Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 RF1LE RF1FE RF1WE RF1NE RF0LE RF0FE RF0WE RF0NE Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 29 – ARAE Access to Reserved Address Enable
Bit 28 – PEDE Protocol Error in Data Phase Enable
Bit 27 – PEAE Protocol Error in Arbitration Phase Enable
Bit 26 – WDIE Watchdog Interrupt Interrupt Enable
Bit 25 – BOE Bus_Off Status Interrupt Enable
Bit 24 – EWE Warning Status Interrupt Enable
Bit 23 – EPE Error Passive Interrupt Enable
Bit 22 – ELOE Error Logging Overflow Interrupt Enable
Bit 21 – BEUE Bit Error Uncorrected Interrupt Enable
Bit 20 – BECE Bit Error Corrected Interrupt Enable
Bit 19 – DRXE Message stored to Dedicated Rx Buffer Interrupt Enable
Bit 18 – TOOE Timeout Occurred Interrupt Enable
Bit 17 – MRAFE Message RAM Access Failure Interrupt Enable
Bit 16 – TSWE Timestamp Wraparound Interrupt Enable
Bit 15 – TEFLE Tx Event FIFO Element Lost Interrupt Enable
Bit 14 – TEFFE Tx Event FIFO Full Interrupt Enable
Bit 13 – TEFWE Tx Event FIFO Watermark Reached Interrupt Enable
Bit 12 – TEFNE Tx Event FIFO New Entry Interrupt Enable
Bit 11 – TFEE Tx FIFO Empty Interrupt Enable
Bit 10 – TCFE Transmission Cancellation Finished Interrupt Enable
Bit 9 – TCE Timestamp Completed Interrupt Enable
Bit 8 – HPME High Priority Message Interrupt Enable
Bit 7 – RF1LE Rx FIFO 1 Message Lost Interrupt Enable
Bit 6 – RF1FE Rx FIFO 1 FIFO Full Interrupt Enable
Bit 5 – RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable
Bit 4 – RF1NE Rx FIFO 1 New Message Interrupt Enable
Bit 3 – RF0LE Rx FIFO 0 Message Lost Interrupt Enable
Bit 2 – RF0FE Rx FIFO 0 Full Interrupt Enable
Bit 1 – RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable
Bit 0 – RF0NE Rx FIFO 0 New Message Interrupt Enable
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