35.7.1 Control A Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x000 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | PRIV | SWRST | |||||||
| Access | R/W | R/W | R/HC/S | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – RUNSTDBY Run during standby
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The module is internally disabled and stops the operation when all bus transactions are completed. |
| 1 | ENABLE | The module continues the normal operation in Standby sleep mode. |
Bit 2 – PRIV Priveged Access
Bit 0 – SWRST Software Reset
Writing a '1' to this bit will reset all APB registers, including the M_CAN and TSU registers. The bit stays high until reset completes. Setting this bit also sets the SYNCBUSY.SWRST to 1. SYNCBUSY.SWRST stays 1 until reset sequence completes.
| Value | Name | Description |
|---|---|---|
| 0 | NONE | No Action. |
| 1 | RESET | Reset all APB registers. |